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CXP85112B/85116B CXP85220A/85224A/85228A/85232A
CMOS 8-bit Single-chip Microcomputer
Description The CXP85112B/85116B, CXP85220A/85224A/ 85228A/85232A is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, vector interruption, on-screen display function, I2C bus interface, PWM generator, remote control reception circuit, HSYNC counter, power source frequency counter and watch dog timer besides the basic configurations of 8-bit CPU, ROM, RAM, and l/O port. The CXP85112B/85116B, CXP85220A/85224A/ 85228A/85232A also provides a power-on reset function and a sleep function that enables lower power consumption. 64 pin SDIP (Plastic) 64 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 1s at 4MHz operation * Incorporated ROM capacity 12K bytes (CXP85112B) 16K bytes (CXP85116B) 20K bytes (CXP85220A) 24K bytes (CXP85224A) 28K bytes (CXP85228A) 32K bytes (CXP85232A) * Incorporated RAM capacity 352 bytes (CXP85112B/85116B) 448 bytes (CXP85220A/85224A/85228A/85232A) * Peripheral functions -- On-screen display function 12 x 16 dots, 128 types 21 words x 4 Iines (more than 4 Iines possible) Double scan mode compatible, jitter elimination circuit -- I2C bus interface -- PWM output 14 bits, 1 channel 6 bits, 8 channels -- Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO -- A/D converter 4 bits, 4channels, successive approximation method (Conversion time of 40s/4MHz) -- HSYNC counter -- Power supply frequency counter -- Watch dog timer -- Serial I/O 8-bit clock synchronization -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer * Interruption 14 factors, 14 vectors, multi-interruption possible * Standby mode Sleep * Package 64-pin plastic SDIP/QFP * Piggyback/evaluation chip CXP85100A, CXP85190 (Custom font compatible) CXP85200A, CXP85290 (Custom font compatible)
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E93Z17B86
Block Diagram
PE1/INT1 PD0/INT2
EXTAL
XTAL MP
PE0/INT0
RST
VDD
VSS
EXLC XLC B G R BLK HSYNC VSYNC
ON SCREEN DISPLAY
PORT A
2
SPC700 CPU CORE
CLOCK GEN./ SYSTEM CONTROL
PA0 to PA7
PD6/RMC
REMOCON
FIFO
PORT C
PD7/EC PE7/TO
TIMER/COUNTER
INTERRUPT CONTROLLER
PD3/SI PD2/SO PD1/SCK ROM 12K/16K/20K/24K/28K/32K BYTES RAM 352/448 BYTES
SERIAL I/O
PORT B
2
PB0 to PB7
PC0 to PC7
PD4/HSI WATCH DOG TIMER
HSYNC COUNTER PRESCALER/ TIME BASE TIMER PE0 to PE5 PE6 to PE7
PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 14 BIT PWM
I2C INTERFACE UNIT
6 BIT PWM 8CH
PE6/PWM
PF0/PWM0 to PF7/PWM7
PORT F
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
PE2/AN0 to PE5/AN3
A/D CONVERTER
PORT E
PD5/ACI
AC TIMER
PORT D
-2-
PD0 to PD7
PF0 to PF7
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Assignment 1 (Top View) 64 pin SDIP Package
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7/EC PD6/RMC PD5/ACI PD4/HSI PD3/SI PD2/SO PD1/SCK VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD NC VSS MP PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 BLK R G B VSYNC HSYNC EXLC XLC PE0/INT0 PE1/INT1 PE2/AN0 PE3/AN1 PE4/AN2 PE5/AN3 PE6/PWM PE7/TO RST EXTAL XTAL PD0/INT2
Note)
1. NC (Pin 63) must be connected to VDD. 2. Vss for both Pins 32 and 62 must be grounded. 3. MP (Pin 61) must be connected to GND.
-3-
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Assignment 2 (Top View) 64 pin QFP Package
PA3
PA4
PA5
PA6
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52
PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7/EC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
NC
MP
PF0/PWM0
PA7
PF1/PWM1
PA2
VSS
PF2/PWM2
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PF3/PWM3 PF4/PWM4/SCL0 PF5/PWM5/SCL1 PF6/PWM6/SDA0 PF7/PWM7/SDA1 BLK R G B VSYNC HSYNC EXLC XLC PE0/INT0 PE1/INT1 PE2/AN0 PE3/AN1 PE4/AN2 PE5/AN3
20 21 22 23 24 25 26 27 28 29 30 31 32
PD2/SO
PD3/SI
PD4/HSI
PD0/INT2
PD5/ACI
EXTAL
XTAL
RST
Note)
1. NC (Pin 56) must be connected to VDD. 2. Vss for both Pins 26 and 58 must be grounded. 3. MP (Pin 55) must be connected to GND.
-4-
PE6/PWM
PD6/RMC
VSS
PD1/SCK
PE7/TO
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Description Symbol PA0 to PA7 I/O I/O Description (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) External interruption request input. Active at falling edge. (Port D) 8-bit I/O port. I/O can be set ina a unit of single bits. Capable of driving 12mA sink current. (8 pins) Serial clock I/O. Serial data output. Serial data input. HSYNC counter input. Input for power supply frequency counter. Input for remote control reception circuit. External event input for timer/counter. External interruption request inputs. Active at falling edge. (2 pins) (Port E) Analog inputs for A/D converter. 8-bit port. Lower (4 pins) 6 bits are for inputs; upper 2 bits are for 14-bit PWM output. outputs. (CMOS output) Rectangular waveform output for Timer 1. (Duty output 50%) (Port F) 6-bit PWM outputs. 8-bit output port, (8 pins) operating as N-ch open drain output for high current Transfer clock I/Os for I2C bus (12mA). interface. Lower 4 bits are medium voltage drive outputs (12V), upper 4bits are 5V Transfer data I/Os for I2C data bus. drive outputs. (8 pins) 4-bit outputs for CRT display. Horizontal synchronizing signal input for CRT display. Vertical synchronizing signal input for CRT display. -5-
PB0 to PB7
I/O
PC0 to PC7
I/O
PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC PE0/INT0 PE1/INT1 PE2/AN0 to PE5/AN3 PE6/PWM PE7/TO PF0/PWM0 to PF3/PWM3 PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 R, G, B, BLK HSYNC VSYNC
I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input Input/Input
Input/Input
Output/Output Output/Output
Output/Output
Output/Output/ I/O
Output/Output/ I/O Output Input Input
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Symbol EXLC XLC EXTAL XTAL RST MP VDD Vss Input
I/O
Description Clock oscillation I/Os for CRT display. Oscillation frequency is set using the external L and C. Crystai connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active, system reset. RST is an I/O, from whlch Low level is output when the built-in power-on reset function is activated at the rise of power on. (Mask option) Microprocessor mode input. For this device, this pin must be grounded. Vcc supply. GND. Both Vss must be grounded.
Output Input Output I/O Input
-6-
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Input/Output Circuit Formats for Pins Pin Port A Port B Port C PA0 to PA7 PB0 to PB7 PC0 to PC7
Data for Ports A, B, and C
Circuit format
When reset
Direction for Ports A, B, and C IP Data bus Input protection circuit
Hi-Z
RD (Ports A, B, and C)
24 pins Port D
PD0/INT2 PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC
Port D data Port D direction High current 12mA IP RD (Port D) INT2, SI, HSI, ACI, RMC, EC Schmitt input
Hi-Z
Data bus
6 pins Port D
SCK or SO Output eneble
High current 12mA
PD1/SCK PD2/SO
Port D data Port D direction Schmitt input
IP
Hi-Z
Data bus RD (Port D) SCK only
2 pins
-7-
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Port E PE0/INT0 PE1/INT1 2 pins Port E
IP
Circuit format
Schmitt input (To interruption circuit)
When reset
Hi-Z
Data bus RD (Port E)
Input multiplexer
PE2/AN0 to PE5/AN3
IP
To A/D converter
Hi-Z
Data bus
4 pins Port E PE6/PWM PE7/TO
TO, PWM
RD (Port E)
Port E data
High level
2 pins
Port selection
Port F
PWM
PF0/PWM0 to PF3/PWM3
Middle tension proof 12V Port F data Port selection High current 12mA
Hi-Z
4 pins Port F
SCL, SDA
PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1
I2C output enable PWM
Hi-Z
Port F data Port selection SCL, SDA (To I2C circuit) IP Schmitt input BUS SW To other I2C pins
4 pins -8-
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin BLK R G B 4 pins
BLK, R, G, B
Circuit format
When reset
Output polarity Hi-Z output active by writing into the output polarity register.
Hi-Z
Schmitt input
HSYNC VSYNC
IP
HSYNC VSYNC
Hi-Z
2 pins
Input polarity
EXLC XLC
EXLC
IP
Oscillation control
Oscillation terminated
XLC IP CRT display clock
2 pins
EXTAL XTAL
EXTAL
IP
* Diagram shows circuit composition during oscillation. * Feedback resistor is removed during stop.
Oscillation
2 pins
XTAL
Pull-up resistance
RST
Mask option OP
Schmitt input
Low level
1 pin
From power-on reset circuit (Mask option)
MP
IP CPU mode
Hi-Z
1 pin
-9-
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Medium voltage drive output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation Symbol VDD VIN VOUT VOUTP IOH IOH IOL IOLC IOL Topr Tstg PD Rating -0.3 to +7.0 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +15.0 -5 -50 15 20 130 -20 to +75 -55 to +150 1000 600 Unit V V V V mA mA mA mA mA C C mW mW SDIP QFP
(Vss = 0V reference) Remarks
Pins PF0 to PF3
Total for all output pins Excludes high current outputs High current outputs2 Total for all output pins
1 VIN and VOUT must not exceed VDD + 0.3V. 2 The high current operation transistor is the N-ch transistor of PD and PF0 to PF3. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Symbol Min. 4.5 Supply voltage VDD 3.5 2.5 VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 VDD VDD Unit V V V V V V V V V C (Vss = 0V reference) Remarks Guaranteed operation range Low-speed mode guaranteed operation range1 Guaranteed data hold range during stop Includes I2C Schmitt input2 CMOS Schmitt input3 EXTAL4 Includes I2C Schmitt input2 CMOS Schmitt input3 EXTAL4
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.4 +75
1 Specifies only for 1/16 frequency demultiplication mode and sleep mode. 2 Value for each pin of normal input ports (PA, PB, PC, PE2 to PE5), PF4 to PF7, and MP. 3 Value of the following pins: PD0/lNT2, PD1/SCK, PD2, PD3/Sl, PD4/HSl, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/lNT1, HSYNC, VSYNC, RST. 4 Specifies only during external clock input. - 10 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Electrical Characteristics DC Characteristics Item High level output current Symbol VOH Pins PA to PD, PE6, PE7, R, G, B, BLK PA to PD, PE6, PE7, R, G, B, BLK, PF0 to PF3, RST1 Low level output current VOL PD, PF0 to PF3 PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) IIHE Input current IIHL IILR I/O leakage current Open drain output leakage current (N-ch Tr in off state) IIZ RST2 PA to PE, HSYNC, VSYNC, R, G, B, BLK, RST2, MP PF0 to PF3 ILOH PF4 to PF7 SCL0: SCL1 SDA0: SDA1 EXTAL (Ta = -20 to +75C, Vss = 0V reference) Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V VDD = 5.5V VI = 0, 5.5V VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V Operation mode3 (1/2 frequency demultiplier clock) 4MHz crystal oscillation (C1 = C2 = 22pF) All outputs open Sleep mode Stop mode4 Pins other than VDD and Vss Clock 1MHz 0V for all pins excluding 0.5 -0.5 -1.5 Min. 4.0 3.5 0.4 0.6 1.5 0.4 0.6 40 -40 -400 10 50 10 120 Typ. Max. Unit V V V V V V V A A A A A A
Impedance connected RBS to I2C bus switch (output Tr in off state)
IDD Power supply current IDDSL IDDST Input capacity CIN VDD3
8
20
mA
0.5 -- -- 10
2 -- 20
mA A pF
1 RST specifies only when the power-on reset circuit has been selected througn mask option. 2 RST specifies input current when the pull-up resistance has been selected; Ieakage current when no resistance has been selected. 3 Specifies only when the oscillatlon of OSD has been terminated. 4 This device does not enter the stop mode.
- 11 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event clock input clock pulse width Event count input clock rise time, fall time 1 Symbol fC Pins XTAL EXTAL EXTAL EXTAL EC EC
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 Min. 3.5 100 200 Max. 4.5 Unit MHz ns ns ns 20 ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
tsys + 501
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
OPEN
Fig. 2. Clock applying condition
0.8VDD EC 0.2VDD
tEH
tEF
tEL
tER
Fig. 3. Event count clock timing
- 12 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(2) Serial transfer Item SCK cycle time SCK High and Low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Symbol Pins SCK
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode Min. 1000 8000/fc 400 4000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
SCK
SCK input mode SCK output mode
SI
SCK input mode SCK output mode
SI
SCK input mode SCK output mode
SO
SCK input mode SCK output mode
Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.
tKCY tKL tKH
0.8VDD SCK 0.2VDD
tSIK
tKSI
0.8VDD SI Input data 0.2VDD
tKSO
0.8VDD SO 0.2VDD Output data
Fig. 4. Serial transfer timing
- 13 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(3) Interruption, reset input (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item External interruption High and Low level widths Reset input Low level width Symbol Pins INT0 to INT2 RST Conditions Min. 1 8/fc Max. Unit s s
tIH tIL tRSL
tIH
tIL
INT0 to INT2 (Falling edge)
0.8VDD 0.2VDD
Fig. 5. Interruption input timing
tRSL
RST 0.2VDD
Fig. 6. RST input timing
(4) Power on reset Power on reset Item Power supply rise time Power supply cut-off time
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins Conditions Power-on reset Repetitive power-on reset Min. 0.05 1 Max. 50 Unit ms ms
tR tOFF
VDD
Specifies only when the power-on reset function has been selected.
VDD
4.5V 0.2V 0.2V tR The power supply should be raised smoothly. tOFF
Fig. 7. Power-on reset - 14 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(5) A/D converter characteristics Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage VZT1 VFT2 Symbol Pin
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Min. Typ. Max. 4 1 Ta = 25C VDD = 5.0V Vss = 0V -10 4370 160/fc 12/fc 160 4530 320 4690 Unit Bits LSB mV mV s s VDD V
tCONV tSAMP
VIAN AN0 to AN3
0
FH EH
Digital conversion value
Linearity error 1H 0H VZT Analog input VFT
1 VZT: Value at which the digital conversion value changes from 0H to 1H and vice versa. 2 VFT: Value at which the digital conversion value changes from EH to FH and vice versa.
Fig. 8. Definition of A/D converter terms Note) The 4-bit conversion specifies values based on the upper 5 bits of the A/D data register (ADD: Address 00F5H), compensated into 4-bit data. A program example is shown below: (A/D converter program example) MOV A, ADD LSR A LSR A LSR A LSR A ADC A, #00H CMP A, #10H BNE ADC_SKIP MOV A, #0FH ADC_SKIP:
; ACC conversion data ; Shift to the right (4 times) ; ; ; ; Addition with carry (data increment if AD3 = 1) ; ; ;
- 15 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(6) I2C bus timing Item SCL clock frequency Bus free time prior to transfer start Transfer start hold time Clock Low level width Clock High level width Setup time during repetitive transfer Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Transfer end setup time Symbol fSLC
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pins SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 Conditions Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 1 300 Max. 100 Unit kHz s s s s s s ns s ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 The data hold time does not take into consideration SCL rise time (300ns max.). Ensure that the data hold time exceeds 300ns.
SDA tBUF tR tF tHD; STA
SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P
Fig. 9. I2C bus transfer timing
I2C device
I2C device
RS SDA0 (or SDA1) SCL0 (or SCL1)
RS RS
RS RP
RP
Fig. 10. Recommended circuit example for I2C device
* Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * Serial resistance (Rs = 300 and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused by CRT flashover.
- 16 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(7) OSD (On-Screen Display) timing (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item OSD clock frequency HSYNC pulse width VSYNC pulse width HSYNC after-edge rise time/fall time VSYNC after-edge rise time/fall time * H indicates 1HSYNC period.
tHCG
Symbol fOSC
Pins EXLC XLC HSYNC VSYNC HSYNC VSYNC
Condition Fig. 12 Fig. 11 Fig. 11 Fig. 11 Fig. 11
Min. 4 1.2 1.0
Max. 13
Unit MHz s H*
tHWD tVWD tHCG tVCG
200 1.0
ns s
tHWD
HSYNC when Bit 5 of OPOL register (01FBH) is set to "0"
0.8VDD
0.2VDD
tVWD
tVCG
VSYNC when Bit 4 of OPOL register (01FBH) is set to "0"
0.8VDD
0.2VDD
Fig. 11. OSC timing
EXLC
XLC
L
C1
C2
Fig. 12. LC oscillation circuit example
- 17 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Supplement (i) (ii)
EXTAL
XTAL Rd
EXTAL
XTAL Rd
C1
C2 C1 C2
Fig. 13. Recommended Oscillation circuit Circuit example (i) 30 30 0 (ii)
Manufacturer
Model CSA4.00MG
fc (MHz) 4.00 4.19 4.00 4.19 4.00 4.19
C1 (pF)
C2 (pF)
Rd ()
MURATA MFG CO., LTD.
CSA4.19MG CST4.00MGW CST4.19MGW HC-49/U03
RIVER ELETEC CORPORATION KINSEKI LTD.
10
10
0 (i)
HC-49/U (-S)
4.00 4.19
18
18
0
Indicates types with on-chip grounding capacitance (C1 and C2).
Mask option table Item Reset pin pull-up resistance Power-on reset circuit Content Non-existent Non-existent Existent Existent
- 18 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
IDD vs. VDD
(fc = 4MHz, Ta = 25C typical) 15 10 1/2 frequency demultiplication mode 1/4 frequency demultiplication mode 12 11 10 9
IDD vs. fc
(VDD = 5V, Ta = 25C typical) 1/2 frequency demultiplication mode
IDD - Power supply current [mA]
IDD - Power supply current [mA]
1/16 frequency demultiplication mode 1 Sleep mode
8 7 6 5 4 3 2 1/16 frequency demultiplication mode 1/4 frequency demultiplication mode
0.1
1 Sleep mode 0 2 3 4 5 6 VDD - Supply voltage [V] 1 2 3 4 5 6
fc - System clock [MHz]
OSD oscillation vs. C Calculated curves
(reference value by theoretical calculation) 100
L - Inductasce [H]
5.0MHz 6.5MHz
10
13.0MHz
fosc = 1 0
1 2 50 LC
C = C1//C2
100
C1, C2 - Capacitance [pF]
Fig. 14. Characteristics curves - 19 -
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Package Outline
Unit: mm
64PIN SDIP (PLASTIC)
+ 0.4 57.6 - 0.1 64 33
19.05 + 0.3 17.1 - 0.1
+ 0.1 0.05 0.25 -
0 to 15 32 1.778 0.5 0.1 0.9 0.15
1
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-64P-01 SDIP064-P-0750 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 8.6g
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
3.0 MIN
0.5 MIN + 0.4 4.75 - 0.1
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
+ 0.35 2.75 - 0.15 0.2 M 0 to10
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g
- 20 -
0.8 0.2
19
16.3

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